ECS527U : Lab3 2022/23
School of Electronic Engineering and Computer Science
ECS527U: Digital System Design
Lab 3: 16-bit Synchronous Up/Down Counter – Modelling & Simulation
Introduction
Synchronous counter is a classic sequential circuit that is constructed with storage elements like flip-flops and
combinational circuits. In this lab, you will model a bit slice for the synchronous counter using behaviour
modelling, then construct a 16-bit up or down counter using the structural modelling technique in VHDL.
You will also practise the skill of writing a VHDL testbench and test your design using the Xilinx ISim simulator.
After completing this lab, you should be able to:
Understand a VHDL process that describe a D flip-flop.
Understand the meaning of both structural modelling in VHDL.
Simulate and test your circuit using Xilinx ISE Simulator (ISim) and testbench(es).
Restriction: only the following VHDL package(s) and feature(s) is/are allowed in any of your circuit model
design files (testbenches excluded) for this lab.
IEEE.std_logic_1164.all ONLY
Intermediate signals, logic operators, relational operators
Signal assignment statements, conditional signal assignment statements (when-else, with-select)
Port map statements
Process statements, if-else statements, case statements
16-bit Synchronous Up/Down Counter: Specification
A digital sequential circuit is synchronous when the output bits change only in certain discrete time, commonly
at the positive edge of the clock signal.
Synchronous counter can be designed using a basic idea: D flip-flops store the count (in binary) while an adder
calculates the next count at the input of the flip-flops. Therefore at the clock edge, the next count becomes
the current count and all flip-flops are always synchronised.
You will be using VHDL to model a counter that works as follows:
a clock signal CLK controls the rate of count. At every clock edge, the counter counts up or down, when
it is enabled with EN = 1;
it counts up when U/D (U_Dn in VHDL) = 1, down otherwise;
the output Q is a 16-bit unsigned integer;
CLR (CLRn in VHDL) clears the output to 0 asynchronously (i.e. anytime, even outside the clock edge).
Page 1 of 4
ECS527U : Lab3 2022/23
The following table summarises the function of the counter (× means don’t care):
CLR EN U/D CLK Description
0 × × × Q = 0, cleared to 0
1 0 × × Q unchanged
1 1 1 +ve edge Q = Q + 1
1 1 0 +ve edge Q = Q 1
Task 1: Bit Slice Modelling and Simulation
You are provided with a bit-slice block named SyncCountBit which will be used to construct the 16-bit counter
in the next Task. Its structure is shown in the following diagram:
Write the VHDL model for this bit slice following the steps below:
Download the given project ECS527U-23_Lab3.zip from QMPlus
Extract the whole archive to a working directory (e.g. One Drive, Documents, etc.)
Open the project with Xilinx Vivado.
Study the provided VHDL files carefully.
Create a new file SyncCountBit.vhd and write your VHDL codes based on the circuit shown above.
The standard full adder has already been provided in FA.vhd.
Use the tools to help check the syntax of your VHDL.
Once completed, proceed to the next task “testbench design and simulation”.
Task 2: Testbench Design and Simulation
Now look at the sources for “Simulation”
Create a new VHDL testbench called SyncCountBit_tb.vhd that takes SyncCountBit as the unit under
test (UUT). Set the testbench as the top module so that simulat
ion will be run on this.
Add VHDL statements to the testbench to generate stimuli that can test all functions (consider the
possible combinations of the inputs) of the module.
Simulate the testbench and check the waveform. If anything is wrong, check the VHDL code (of your
module or testbench) and repeat the process.
Once completed, proceed to the next task.
Page 2 of 4
ECS527U : Lab3 2022/23
Task 3: Complete the Counter and Lab Board Verification
You can now complete the design in the module BB_core.
Write port map statements (preferably with a for-generate statement) to create sixteen instances of SyncCountBit
and connect them along the carry ins and outs to make a 16-bit counter. The input X, the clock signal CLK and
the clear signal CLRn are shared by all instances, as shown below.
Next, you need to work out the value of X and the first carry in Ci0 such that the enable and up/down function
of the counter can be realised. The following table is useful:
EN U/D X(15), . . . , X(0) Ci0
0 0 1…1 1
0 1 0…0 0
1 0 1…1 0
1 1 0…0 1
You may need to study the related lecture notes and tutorial exercises for further details.
Finally, add signal assignments to complete the following connections to the input and output devices.
Devices Signals
input: sw(2) CLR (CLRn)
input: sw(1) EN
input: sw(0) U/D (U_Dn)
output: led(0) Co
output: ss3 Q(15 : 12)
output: ss2 Q(11 : 8)
output: ss1 Q(7 : 4)
output: ss0 Q(3 : 0)
When you are done, you may further simulate the counter with the testbench BB_core_tb provided. Check the
waveform to confirm that the outputs are correct in the simulator. Feel free to modify the testbench.
Once you synthesise and implement the top module BB_top and generate the bitstream (BB_Top.bit) following
the Vivado design flow.
Page 3 of 4
ECS527U : Lab3 2022/23
Locate your bitstream file (usually inside the “ECS527U-23_Lab3.runsimpl_1” folder) and then copy the
bitstream file to another path that contains no spaces (.) nor commas (,). (e.g. G:) before continuing with the
following steps.
When the bitstream is ready, you can ask Vivado to download the design to the lab board by following the steps:
Connect USB cable to the lab board and the PC.
Power on the lab board (the power switch is at the upper-left corner.)
Choose “Open Hardware Manager”, “Open Target”, then auto-detect to the lab board
Program device (Spartan FPGA xc7s50) with the bitstream “BB_Top.bit”.
Please note the clock signal in BB_core had been scaled down to around 4 Hz such that the counting
becomes visible.
Once you program the lab board, you can verify your design by checking against the function table on page 2.
Reference: Final Hierarchy of VHDL Design Files
You should be able to see this hierarchy when all VHDL codes had been completed.
BB_Top.vhd
________ (BB_core.vhd) <- BB_core_tb.vhd {testbench}
|
_______________ [SyncCountBit.vhd] <--- [SyncCountBit_tb.vhd] {testbench}
|
________________ FA.vhd
[xxx.vhd]: VHDL files for you to create and work on
(yyy.vhd): VHDL files that you may need to modify
Submission
Submit the following files to QMPlus:
1. VHDL files: SyncCountBit.vhd, SyncCountBit_tb.vhd, BB_core.vhd
2. 200-250 words of writing to conclude what you have learned from this lab exercise.
This lab exercise is formative but your attendance and submission is mandatory. Your submission will be marked
with feedbacks in order to prepare for the assessed lab test.
Deadline: 28th March, 2023 Tuesday 12:00 noon
– End of Lab 3 –
Page 4 of 4